The present invention relates to a semiconductor integrated circuit, and more particularly to a data output buffer for outputting data read from a cell array to circuitry externally to a chip.
As the density of a semiconductor integrated circuit becomes higher and the operating speed thereof increases, noise reduction becomes a more critical factor. There are many reasons that cause the semiconductor integrated circuit to generate noise. Most significantly, noise is generated at an output stage of a data output buffer (this is commonly known as a "data output driver") when the data read from a memory cell passes through an input/output line sense amplifier formed on a data input/output line and then travels externally to the chip. Since a transistor constituting the output stage of the data output buffer functions to buffer internal and external impedance, and has a large size channel in comparison with those of other components within the chip in order to access data at a high speed, a great amount of current flows instantaneously when a data output operation is performed (at this moment, a transition is made from the "high" level to the "low" level, or from the "low" level to the "high" level). As a result, ground noise is generated at the circuits which are supplied with a ground voltage as a power supply voltage on the same chip.
FIG. 1 shows a conventional data output buffer which is well known in the art. In FIG. 1, DO and DO represent data inputs read from a memory cell, and CLK represents a clock signal for enabling a pull-up and pull-down controller 100 of the data output buffer. Further, PU and PD output from the pull-up and pull-down controller 100 are applied respectively to pull-up and pull-down transistors 2 and 4 constituting the output stage of the data output buffer, to transfer the data output DOUT of the data output buffer to a data output pad (PAD or PIN: not shown). The components of the pull-up and pull-down controller 100 are not shown in FIG. 1 because the construction thereof is well known in the art.
The operation of FIG. 1 will be explained with reference to FIG. 2, showing an operational timing diagram thereof. First, the operation in which the data output DOUT of the "high" level is output will be explained. When an output operation of the data output buffer is disabled, the signals PU and PD are all at the "low" level, thereby causing the pull-up and pull-down transistors 2 and 4 to be turned off. In the meantime, if an external address changes to generate a data output DOUT of a "high" level, and the clock signal CLK goes to an activate "high" state, the pull-up and pull-down controller 100 is enabled, and the pull-up transistor 2 is turned on by the signals PU and PD respectively set to the "high" level and the "low" level according to the data inputs DO and DO. As a result, the voltage at an output node 6 goes to the "high" level. Thus, the data output DOUT of the "high" level is output, and a large amount of current flows instantaneously from a power supply voltage Vcc into a channel of the pull-up transistor 2.
Next, the operation in which the data DOUT of the "low" level is output will be explained. If the external address changes to generate the data output DOUT of the "low" level and the signal CLK goes to the active "high" state, the pull-up and pull down controller 100 is enabled. Thus, the pull-down transistor 4 is turned on by the signals PU and PD set respectively to the "low" level and the "high" level according to the data inputs DO and DO, thereby causing a voltage at an output node 6 to be discharged to the ground voltage Vss through a channel of the pull-down transistor 4. Therefore, the data output DOUT of the "low" level is output. At this moment, a large amount of the current flows instantaneously through the channel of the pull down transistor 4, generating the ground noises as shown in FIG. 2.
The ground noises generated by the current flowing into the ground line Vss causes error data at the output node 6 as shown in FIG. 2, resulting in a faulty operation of the system. Such undesirable operation is preformed through the large channel of the pull-down transistor 4 whenever the circuit outputs the "low" state, so that the operating speed of the chip is lowered and the chip performs the incorrect operation. This problem becomes serious in the high density semiconductor integrated circuit having a large number of the data output buffers within one chip such as a byte wide integrated circuit. Further, as the load of the output stage of the data output buffer become larger, the time required for a data transition is delayed longer.
In order to solve this problem, the data output buffer having a preset circuit formed in the output stage is disclosed in Korean Patent Application No. 1991-24802 filed on 28 Dec. 1991 by the same applicant, and hereby incorporated by reference. Here, the ground noises are removed by presetting an output line of the data output buffer with a predetermined voltage during the data output operation. However, such device is disadvantageous in that a number of data output buffers each should include (on the same chip) the preset circuits, according to the bit-wide memory trends of recently developed semiconductor integrated circuits. Since the preset circuit included in each data output buffer needs a control signal, it should have an extra circuit for generating the control signal. In this arrangement, the area occupied by the preset circuit on the chip is rather large. This is disadvantageous for the high density of the very large scale integrated circuit. In addition, under such circuit construction, the ground noises are not satisfactorily prevented from being generated at the ground line when the data output at the "low" level is output.